PCI configuration registers: Common header: 0x00: 0x5b641002 0x00100047 0x03800080 0x00000040 Vendor Name: ATI Technologies (0x1002) Device Name: FireGL V3100 (RV370) 5B64 (0x5b64) Command register: 0x0047 I/O space accesses: on Memory space accesses: on Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: on Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Interrupt disable: off Status register: 0x0010 Immediate Readiness: off Interrupt status: inactive Capability List support: on 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: off Data parity error detected: off DEVSEL timing: fast (0x0) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: display (0x03) Subclass Name: miscellaneous (0x80) Interface: 0x00 Revision ID: 0x80 BIST: 0x00 Header Type: 0x00 (0x00) Latency Timer: 0x00 Cache Line Size: 256bytes (0x40) Type 0 ("normal" device) header: 0x10: 0x10000008 0x00000001 0x00100000 0x00000000 0x20: 0x00000000 0x00000000 0x00000000 0x0e55530c 0x30: 0x00120000 0x00000050 0x00000000 0x000001ff Base address register at 0x10 type: 32-bit prefetchable memory base: 0x10000000 Base address register at 0x14 type: I/O base: 0x00000000 Base address register at 0x18 type: 32-bit nonprefetchable memory base: 0x00100000 Base address register at 0x1c not implemented Base address register at 0x20 not implemented Base address register at 0x24 not implemented Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x530c Subsystem ID: 0x0e55 Expansion ROM Base Address Register: 0x00120000 base: 0x00120000 Expansion ROM Enable: off Validation Status: Validation not supported Validation Details: 0x0 Capability list pointer: 0x50 Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x01 (pin A) Interrupt line: 0xff Capability register at 0x50 type: 0x01 (Power Management) Capability register at 0x58 type: 0x10 (PCI Express) PCI Power Management Capabilities Register Capabilities register: 0x0602 Version: 1.1 PME# clock: off Device specific initialization: off 3.3V auxiliary current: self-powered D1 power management state support: on D2 power management state support: on PME# support D0: off PME# support D1: off PME# support D2: off PME# support D3 hot: off PME# support D3 cold: off Control/status register: 0x00000000 Power state: D0 PCI Express reserved: off No soft reset: off PME# assertion: disabled Data Select: 0 Data Scale: 0 PME# status: off Bridge Support Extensions register: 0x00 B2/B3 support: off Bus Power/Clock Control Enable: off Data register: 0x00 PCI Express Capabilities Register Capability register: 0x0001 Capability version: 1 Device type: PCI Express Endpoint device Slot implemented: off Interrupt Message Number: 0x00 Device Capabilities Register: 0x00000260 Max Payload Size Supported: 128 bytes max Phantom Functions Supported: not available Extended Tag Field Supported: 8bit Endpoint L0 Acceptable Latency: 64ns to less than 128ns Endpoint L1 Acceptable Latency: 1us to less than 2us Attention Button Present: off Attention Indicator Present: off Power Indicator Present: off Role-Based Error Report: off Captured Slot Power Limit: 0W Function-Level Reset Capability: off Device Control Register: 0x0810 Correctable Error Reporting Enable: off Non Fatal Error Reporting Enable: off Fatal Error Reporting Enable: off Unsupported Request Reporting Enable: off Enable Relaxed Ordering: on Max Payload Size: 128 byte Extended Tag Field Enable: off Phantom Functions Enable: off Aux Power PM Enable: off Enable No Snoop: on Max Read Request Size: 128 byte Device Status Register: 0x0000 Correctable Error Detected: off Non Fatal Error Detected: off Fatal Error Detected: off Unsupported Request Detected: off Aux Power Detected: off Transaction Pending: off Emergency Power Reduction Detected: off Link Capabilities Register: 0x00001d01 Maximum Link Speed: 2.5GT/s Maximum Link Width: x16 lanes Active State PM Support: L0s and L1 supported L0 Exit Latency: 64ns to less than 128ns L1 Exit Latency: Less than 1us Port Number: 0 Clock Power Management: off Surprise Down Error Report: off Data Link Layer Link Active: off Link BW Notification Capable: off ASPM Optionally Compliance: off Link Control Register: 0x0000 Active State PM Control: disabled Read Completion Boundary Control: 64bytes Link Disable: off Retrain Link: off Common Clock Configuration: off Extended Synch: off Enable Clock Power Management: off Hardware Autonomous Width Disable: off Link Bandwidth Management Interrupt Enable: off Link Autonomous Bandwidth Interrupt Enable: off DRS Signaling Control: not reported Link Status Register: 0x1081 Negotiated Link Speed: 2.5GT/s Negotiated Link Width: x8 lanes Training Error: off Link Training: off Slot Clock Configuration: on Data Link Layer Link Active: off Link Bandwidth Management Status: off Link Autonomous Bandwidth Status: off Device-dependent header: 0x40: 0x00000000 0x00000000 0x00000000 0x0e55530c 0x50: 0x06025801 0x00000000 0x00010010 0x00000260 0x60: 0x00000810 0x00001d01 0x10810000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x00800005 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00000000 0x00000000 0x00000000 0x00000000 0xe0: 0x00000000 0x00000000 0x00000000 0x00000000 0xf0: 0x00000000 0x00000000 0x00000000 0x00000000